CYP15G0401DXB-BGXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CYP15G0401DXB-BGXC' PDF : 53 Pages View PDF
Receive Path Block Diagram
RXLE
BOE[7:0]
RX PLL Enable
Latch
Parity Control
Character-Rate Clock
SDASEL
LPEN
INSELA
INA1+
INA1–
INA2+
INA2–
TXLBA
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
INSELB
INB1+
INB1–
INB2+
INB2–
TXLBB
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
INSELC
INC1+
INC1–
INC2+
INC2–
TXLBC
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
INSELD
IND1+
IND1–
IND2+
IND2–
TXLBD
RBIST[D:A]
FRAMCHAR
RXRATE
RFEN
RFMODE
RXCKSEL
DECMODE
RXMODE[1:0] 2
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Document #: 38-02002 Rev. *L
CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
JTAG
Boundary
Scan
Controller
= Internal Signal
TRSTZ
TMS
TCLK
TDI
TDO
LFIA
8
RXDA[7:0]
RXOPA
3
RXSTA[2:0]
Clock
Select
÷2
RXCLKA+
RXCLKA–
LFIB
8
RXDB[7:0]
RXOPB
3
RXSTB[2:0]
Clock
Select
÷2
RXCLKB+
RXCLKB–
LFIC
8
RXDC[7:0]
RXOPC
3
RXSTC[2:0]
Clock
Select
÷2
RXCLKC+
RXCLKC–
LFID
8
RXDD[7:0]
RXOPD
3
RXSTD[2:0]
Clock
Select
÷2
RXCLKD+
RXCLKD–
2
Bonding
Control
BONDST
BOND_ALL
BOND_INH
MASTER
Page 5 of 53
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