CYW15G0401DXB-BGXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CYW15G0401DXB-BGXC' PDF : 53 Pages View PDF
CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
Table 4. Encoder Bypass Mode (TXMODE[1:0] = LL)
Signal Name
TXDx[0] (LSB)[10]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1] (MSB)
Bus Weight
20
21
22
23
24
25
26
27
28
29
10Bit Name
a
b
c
d
e
i
f
g
h
j
Entry or configuration of the device into these modes will not
damage the device.
TX Mode 3— Word Sync and SCSEL Control of Special Codes
When configured in TX Mode 3, the SCSEL input is captured
along with the associated TXCTx[1:0] data control inputs.
These bits combine to control the interpretation of the
TXDx[7:0] bits and the characters generated by them. These
bits are interpreted as listed in Table 5.
When TXCKSEL = MID, all transmit channels capture data into
their Input Registers using independent TXCLKx clocks. In this
mode, the SCSEL input is sampled only by TXCLKA↑. When
the character (accepted in the Channel-A Input Register) has
passed through the Phase-align Buffer and any selected parity
validation, the level captured on SCSEL is passed to the
Encoder of the remaining channels during this same cycle.
Table 5. TX Modes 3 and 6 Encoding
Characters Generated
X X 0 Encoded data character
0 0 1 K28.5 fill character
1 0 1 Special character code
X 1 1 16-character Word Sync Sequence
To avoid the possible ambiguities that may arise due to the
uncontrolled arrival of SCSEL relative to the characters in the
alternate channels, SCSEL is often used as static control
input.
Word Sync Sequence
When TXCTx[1:0] = 11, a 16-character sequence of K28.5
characters, known as a Word Sync Sequence, is generated on
the associated channel. This sequence of K28.5 characters
may start with either a positive or negative disparity K28.5 (as
determined by the current running disparity and the 8B/10B
coding rules). The disparity of the second and third K28.5
characters in this sequence are reversed from what normal
8B/10B coding rules would generate. The remaining K28.5
characters in the sequence follow all 8B/10B coding rules. The
disparity of the generated K28.5 characters in this sequence
follow a pattern of either ++––+–+–+–+–+–+– or
– – ++ – + – + – + – + – + – +.
When TXMODE[1] = MID (open, TX modes 3, 4, and 5), the
generation of this character sequence is an atomic (non-inter-
ruptible) operation. Once it has been successfully started, it
cannot be stopped until all sixteen characters have been
generated. The content of the associated Input Registers is
ignored for the duration of this 16-character sequence. At the
end of this sequence, if the TXCTx[1:0] = 11 condition is
sampled again, the sequence restarts and remains uninter-
ruptible for the following fifteen character clocks.
If parity checking is enabled, the character used to start the
Word Sync Sequence must also have correct ODD parity.
Once the sequence is started, parity is not checked on the
following fifteen characters in the Word Sync Sequence.
When TXMODE[1] = HIGH (TX modes 6, 7, and 8), the gener-
ation of the Word Sync Sequence becomes an interruptible
operation. In TX Mode 6, this sequence is started as soon as
the TXCTx[1:0] = 11 condition is detected on a channel. In
order for the sequence to continue on that channel, the
TXCTx[1:0] inputs must be sampled as 00 for the remaining
fifteen characters of the sequence.
If at any time a sample period exists where TXCTx[1:0] ≠ 00,
the Word Sync Sequence is terminated, and a character repre-
senting the associated data and control bits is generated by
the Encoder. This resets the Word Sync Sequence state
machine such that it will start at the beginning of the sequence
at the next occurrence of TXCTx[1:0] = 11.
When parity checking is enabled and TXMODE[1] = HIGH, all
characters (including those in the middle of a Word Sync
Sequence) must have correct parity. The detection of a
character with incorrect parity during a Word Sync Sequence
will interrupt that sequence and force generation of a C0.7
SVS character. Any interruption of the Word Sync Sequence
causes the sequence to terminate.
When TXCKSEL = LOW, the Input Registers for all four
transmit channels are clocked by REFCLK.[4] When
TXCKSEL = HIGH, the Input Registers for all four transmit
channels are clocked with TXCLKA↑. In these clock modes all
four sets of TXCTx[1:0] inputs operate synchronous to the
SCSEL input.[11]
TX Mode 4—Atomic Word Sync and SCSEL Control of Word
Sync Sequence Generation
When configured in TX Mode 4, the SCSEL input is captured
along with the associated TXCTx[1:0] data control inputs.
These bits combine to control the interpretation of the
TXDx[7:0] bits and the characters generated by them. These
bits are interpreted as listed in Table 6.
Note:
10. LSB is shifted out first.
11. When operated in any configuration where receive channels are bonded together, TXCKSEL must be either LOW or HIGH (not MID) to ensure that associated
characters are transmitted in the same character cycle.
Document #: 38-02002 Rev. *L
Page 18 of 53
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