CYW15G0401DXB-BGXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CYW15G0401DXB-BGXC' PDF : 53 Pages View PDF
CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
CYP(V)(W)15G0401DXB HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = LOW
tREFCLK
tREFH
tREFL
Note 45
REFCLK
Note 46
tTXCLKO
tTXCLKOD+
tTXCLKOD–
TXCLKO
Switching Waveforms for the CYP(V)(W)15G0401DXB HOTLink II Receiver
Receive Interface
Read Timing
RXCKSEL = LOW
TXRATE = LOW
REFCLK
tREFH
tREFCLK
tREFL
RXDx[7:0],
RXSTx[2:0],
RXOPx
RXCLKA
RXCLKC
Receive Interface
Read Timing
RXCKSEL = LOW
TXRATE = HIGH
REFCLK
tRREFDA
tRREFDV
tREFH
tREFADV+
tREFCDV+
Note 47
tREFADV–
tREFCDV–
tREFCLK
tREFL
tRREFDA
tRREFDV
tRREFDV
tRREFDA
RXDx[7:0],
RXSTx[2:0],
RXOPx
RXCLKA
RXCLKC
tREFADV+
tREFCDV+
Note 47
tREFADV–
tREFCDV–
Note 48
Notes:
47. RXCLKA and RXCLKC are delayed in phase from REFCLK, and are different in phase from each other.
48. When operated with a half-rate REFCLK, the setup and hold specifications for data relative to RXCLKA and RXCLKC are relative to both rising and falling edges
of the respective clock output.
Document #: 38-02002 Rev. *L
Page 40 of 53
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