CYW15G0401DXB-BGXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CYW15G0401DXB-BGXC' PDF : 53 Pages View PDF
CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
Document History Page (continued)
Document Title: CYP(V)(W)15G0401DXB Quad HOTLink II™ Transceiver
Document Number: 38-02002
ECN
REV. No.
Issue
Date
Orig. of
Change
Description of Change
*H 126908 5/12/03
KKV
Corrected footnote 1
Implemented corrections to table format
*I 128365 7/23/03
*J 131897 12/10/03
PDS
PDS
Revised the value of tRREFDV, tREFADV+ and tREFCDV+
When TXCKSEL = MID or HIGH, TXRATE = HIGH is an invalid mode. Made appro-
priate changes to reflect this invalid condition.
Removed requirement of AC coupling for Serial I/Os for interfacing with LVPECL I/Os.
Changed LFIx to Asynchronous output.
Expanded the CDR Range Controller’s permissible frequency offset between incoming
serial signalling rate and Reference clock from ±200-PPM to ±1500-PPM (changed
parameter tREFRX).
Added Table for RXSTx[2:0] status for non-bonded (Independent Channel) mode of
operation for clarity. Separated the Receive BIST status to a new Table for clarity.
Revised Typical Power numbers to match final characterization data.
*K 211429 See ECN KKV Minor change: package diagram disappeared from online pdf
*L 338721 See ECN
SUA
Added CYW15G0401DXB part number for OBSAI RP3 compliance to support
operating data rate upto 1540 MBaud. Made changes to reflect OBSAI RP3 and CPR
compliance. Added Pb-free package option for all parts listed in the datasheet.
Changed MBd to MBaud in SPDSEL pin description
Document #: 38-02002 Rev. *L
Page 53 of 53
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