D950-CORE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'D950-CORE' PDF : 89 Pages View PDF
D950-Core
3: Bit reverse addressing (on X-memory space only) with post-increment
This mode can be selected for AX0, AX1 (see RX0, RX1 bits of STA register).
It generates the bit-reversed address for 2k point FFT implementation (Index
value = 2k-1).
4: Indirect indexed addressing. The address of the operand is the sum of the con-
tents of the address register (AXi, AYi, SPX or SPY) and the contents of the se-
lected index register (IXi or IYi). This addition occurs before the operand is ac-
cessed and therefore requires an extra instruction cycle. The contents of the se-
lected address and index registers are unchanged.
Figures 4.8 and 4.9 show the schematics for indirect addressing with and without post
modification.
Figure 4.8 Indirect Addressing with Post-Modification
address reg.
register
Memory
value
address
- linear
- bit-reverse
- modulo
index reg.
+
VR02017H
Figure 4.9 Indirect Indexed Addressing without Post-Modification
address reg.
+
index reg.
register
Memory
value
- linear
address
VR02017G
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