5.5 Instruction Cycle and Word Count
Table 5.1 Instruction Cycle and Word Count
Instruction Group / Subgroup
Assignment indirect single
Assignment indirect double
Assignment direct
Assignment indirect indexed
Assignment immediate short
Assignment immediate long
Assignment register to register
Assignment register / PRAM
ALU 1-word operand
ALU 2-word operand
ALU 3-word operand
MULT
DMULT
ALU Multiplication
SQR
Bit Manipulation
Program Control Non Delayed
Program Control Delayed
Conditional Assignment
LDCC
REPEAT (single) < 512
REPEAT (single) > 512
REPEAT (block) < 512
REPEAT (block) > 512
COPD
COPS
PUSH / POP register
DPUSH / DPOP register
PUSH / POP direct address
DPUSH / DPOP direct address
PUSH immediate value
DPUSH immediate value
INC SP
Register / Stack indirect indexed
Words
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
2
2 or 3
1
1
1
1
2
2
2
2
1
1
D950-Core
Cycles
1
1
2
2
1
2
1
4
1
1
1
1
2
1
1
2
2 or 3
1 or 2
1
2
1
2
2
2 or 3
1
1
1
1
3
3
3
3
1
2
55/89