DALC208SC6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'DALC208SC6' PDF : 10 Pages View PDF
Technical information
2
Technical information
DALC208
2.1
Note:
Surge protection
The DALC208SC6 is particularly optimized to perform surge protection based on the rail to
rail topology.
The clamping voltage VCL can be calculated as follow :
VCL+ = VREF2 + VF for positive surges
VCL- = VREF1 - VF for negative surges
with
VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
According to the curve Figure 7 we assume that the value of the dynamic resistance of the
clamping diode is typically Rd = 0.7 Ω and VT = 1.2 V.
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg=8 kV, Rg=330 Ω), VREF2 = +5 V,
VREF1 = 0 V, and if in first approximation, we assume that : Ip = Vg / Rg ′ 24 A.
So, we find:
– VCL+′ +23V
– VCL-′ -18V
The calculations do not take into account phenomena due to parasitic inductances.
2.2
Surge protection application example
If we consider that the connections from the pin REF2 to VCC and from REF1 to GND are
done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic
inductances of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs, due
to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr ′ 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 ′ 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be :
– VCL+ = +23 + 144 ′ 167V
– VCL- = -18 - 144 ′ -162V
We can reduce as much as possible these phenomena with simple layout optimization.
It’s the reason why some recommendations have to be followed (See Section 2.3: How to
ensure good ESD protection).
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