DM9008F View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008F' PDF : 68 Pages View PDF
Interrupt Mask Register (IMR)
The Interrupt Mask Register is used to mask interrupts. Each
interrupt mask bit corresponds to a bit in the Interrupt Status
Register (ISR). If an interrupt mask bit is set, an interrupt will be
DM9008
ISA/Plug & Play Super Ethernet Contoller
issued whenever the corresponding bit in the ISR is set. If any
bit in the IMR is set low, an interrupt will not occur when the bit
in the ISR is set. The IMR powers up all zeroes.
7
--
6
RDCE
5
CNTE
4
OVWE
3
TXEE
2
RXEE
1
PTXE
0
PRXE
Bit
Symbol
Description
D0
PRXE PACKET RECEIVED INTERRUPT ENABLE
Enables interrupt when packet is received
D1
PTXE PACKET TRANSMITTED INTERRUPT ENABLE
Enables interrupt when packet is transmitted
D2
RXEE RECEIVE ERROR INTERRUPT ENABLE
Enables interrupt when packet is received with error
D3
TXEE
TRANSMIT ERROR INTERRUPT ENABLE
Enables interrupt when packet transmission results in error
D4
OVWE OVERWRITE WARNING INTERRUPT ENABLE
Enables interrupt when Buffer Management Logic lacks sufficient buffers to store
incoming packet
D5
CNTE COUNTER OVERFLOW INTERRUPT ENABLE
Enables interrupt when MSB of one or more of the Network Tally counters has been set
D6
RDCE DMA COMPLETE INTERRUPT ENABLE
Enables interrupt when Remote DMA transfer has been completed
D7
--
Reserved
Final
21
Version: DM9008-DS-F02
November 30, 2000
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