DM9010 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010
Davicom Semiconductor, Inc.
'DM9010' PDF : 61 Pages View PDF
18.13 HBE
18.12 SQUELCH
18.11 JABEN
18.10 Reserved
18.9-18. Reserved
1
18.0
POLR
1,RW
1, RW
1, RW
0, RW
0, RO
0, RO
DM9010
Single Chip Ethernet Controller with General Processor Interface
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9010 is configured for full duplex operation, this
bit will be ignored (the collision/heartbeat function is invalid in
full duplex mode)
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9010 is in
10BASE-T full duplex or 10BASE-T transceiver Loopback
mode
1 = Jabber function enabled
0 = Jabber function disabled
Reserved
Force to 0, in application.
Reserved
Read as 0, ignore on write
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable
polarity is reversed. This bit is automatically set and cleared by
10BASE-T module
8.11 Power Down Control Register (PWDOR) - 19
Bit Bit Name Default
Description
19.15-19. Reserved 0, RO Reserved
9
Read as 0, ignore on write
19.8 PD10DRV 0, RW Vendor power down control test
19.7 PD100DL 0, RW Vendor power down control test
19.6 PDchip
0, RW Vendor power down control test
19.5 PDcom
0, RW Vendor power down control test
19.4 PDaeq
0, RW Vendor power down control test
19.3
PDdrv
0, RW Vendor power down control test
19.2
PDedi
0, RW Vendor power down control test
19.1 PDedo
0, RW Vendor power down control test
19.0
PD10
0, RW Vendor power down control test
* when selected, the power down value is control by Register 20.0
Preliminary
41
Version: DM9010-17--DS-P04
Jan. 18, 2006
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