DM9010B View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010B
Davicom Semiconductor, Inc.
'DM9010B' PDF : 62 Pages View PDF
DM9010B
Single Chip Ethernet Controller with General Processor Interface
6.9 Back Pressure Threshold Register (08H)
Bit
Name
Default
Description
7:4
BPHW
PHS3, Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
RW when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
:0
JPT
PHS7, Jam Pattern Time. Default is 200us
RW bit3 bit2 bit1 bit0 time
0000
5us
0001
10us
0010
15us
0011
25us
0100
50us
0 1 0 1 100us
0 1 1 0 150us
0 1 1 1 200us
1 0 0 0 250us
1 0 0 1 300us
1 0 1 0 350us
1 0 1 1 400us
1 1 0 0 450us
1 1 0 1 500us
1 1 1 0 550us
1 1 1 1 600us
6.10 Flow Control Threshold Register (09H)
Bit
Name
Default
Description
7:4
HWOT
PHS3, RX FIFO High Water Overflow Threshold
RW Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space.
Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
3:0
LWOT
PHS8, RX FIFO Low Water Overflow Threshold
RW Send a pause packet with pause time=0000 when RX SRAM free space is larger
than this value. This pause packet is enabled after the high water pause packet is
transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM
size
(1 unit=1K bytes)
6.11 RX/TX Flow Control Register (0AH)
Bit
Name
Default
Description
7
TXP0 HPS0,RW TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
6
TXPF HPS0,RW TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
5
TXPEN HPS0,RW Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
Preliminary
21
Version: DM9010B--DS-P01
September 5, 2007
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