DM9013 View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9013
Davicom Semiconductor, Inc.
'DM9013' PDF : 75 Pages View PDF
DM9013
3-port switch with Processor Interface
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7 RESERVED 0,RO Reserved
6 RESERVED P0,WO Reserved
5
CLR1
PH0,RW 0: REG. 01H auto-cleared after read
1: REG. 01H cleared by writing 1 to respected bit.
4:2 RESERVED 0,RO Reserved
1
LBK
PH0, Loopback test Mode
RW
0
RST
PH0,RW Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
Name
Default
Description
7:6 RESERVED 0,RO Reserved
5 RESERVED PH0, Reserved
4 RESERVED 0,RO Reserved
3
TX2END PHS0, TX Packet 2 Complete Status.
RW/C1 This bit is set after transmit completion of packet index 2
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
2
TX1END PHS0, TX Packet 1 Complete status.
RW/C1 This bit is set after transmit completion of packet index 1
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
1:0 RESERVED 0,RO Reserved
6.3 TX Control Register (02H)
Bit
Name
Default
7:4 RESERVED 0,RO
3 CRC_DIS2 PHS0,RW
2 RESERVED 0,RO
1 CRC_DIS1 PHS0,RW
0
TXREQ PHS0,RW
Description
Reserved
CRC Appends Disable for Packet Index 2
Reserved
CRC Appends Disable for Packet Index 1
TX Request. Auto clears after transmit completely
6.4 RX Control Register (05H)
Bit
Name
Default
7 HASHALL PHS0,RW
6 RESERVED PHS0,RW
5 RESERVED PHS0,RW
4 RESERVED PHS0,RW
3
ALL
PHS0,RW
2 RESERVED PHS0,RW
1
PRMSC PHS0,RW
0
RXEN PHS0,RW
Filter All address in Hash Table
Reserved
Reserved
Reserved
Pass All Multicast Packets
Reserved
Promiscuous Mode
RX Enable
Description
Preliminary datasheet
21
DM9013-15-DS-P03
April 9, 2009
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