DRPIC166X View Datasheet(PDF) - Digital Core Design
Part Name
Description
MFG CO.
'DRPIC166X' PDF : 8 Pages View PDF
PERIPHERALS
● Four 8 bit I/O ports
○ Four 8-bit corresponding TRIS registers
○ Interrupt feature on PORTB(7:4) change
● Timer 0
○ 8-bit timer/counter
○ Readable and Writable
○ 8-bit software programmable prescaler
○ Internal or external clock select
○ Interrupt generation on timer overflow
○ Edge select for external clock
● Timer 1
○ 16-bit timer/counter
○ 3-bit prescaler
○ Internal or external clock select
○ Interrupt generation on timer overflow
● Timer 2
○ 8-bit timer with prescaler
● CCP – Compare-Capture-PWM
○ 16 Bit Compare/Capture operations
○ 10-bit resolution PWM output
● USART
○ Asynchronous – full duplex
○ Synchronous – half duplex Master/Slave
● Watchdog Timer
○ Configurable Time out period
○ 7-bit software programmable prescaler
○ Dedicated independent Watchdog Clock input
● Interrupt Controller
○ Seven individually maskable Interrupt sources
○ Two external interrupts – INT Port B[7:4]
change
○ Five internal interrupts – TIMERS 0, 1, 2,
USART
● DoCD™ debug unit
○ Processor execution control
○ Run
○ Halt
○ Step into instruction
○ Skip instruction
○ Read-write all processor contents
All trademarks mentioned in this document
are trademarks of their respective owners.
○ Program Counter (PC)
○ Program Memory
○ Data Memory
○ Special Function Registers (SFRs)
○ Hardware Stack and Stack Pointer
○ Hardware execution breakpoints
○ Program Memory
○ Data Memory
○ Special Function Registers (SFRs)
○ Hardware breakpoints activated at a certain
○ Program address (PC)
○ Address by any write into memory
○ Address by any read from memory
○ Address by write into memory a required data
○ Address by read from memory a required data
○ Three wire communication interface
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC
implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time
restriction except One Year license where
time of use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ Single Design to Unlimited Designs
○ HDL Source to Netlist
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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