DS2890P View Datasheet(PDF) - Dallas Semiconductor -> Maxim Integrated
Part Name
Description
MFG CO.
'DS2890P' PDF : 27 Pages View PDF
DS2890
AC ELECTRICAL CHARACTERISTICS - REGULAR 1-WIRE SPEED
2.8V ≤ VPUP ≤ 6.0V, -40°C ≤ TA ≤ +85°C
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
Time Slot
tSLOT
60
120
µs
Write 1 Low Time
tLOW1
1
15
µs
Write 0 Low Time
tLOW0
60
120
µs
Read Low Time
tLOWR
1
15
µs
Read Data Valid
tRDV
15
µs
1
Release Time
tRELEASE
0
15
45
µs
Read Data Setup
tSU
1
µs
2
Recovery Time
tREC
1
µs
Reset High Time
tRSTH
480
µs
3
Reset Low Time
tRSTL
480
µs
4
Presence Detect High
tPDH
15
60
µs
Presence Detect Low
tPDL
60
240
µs
NOTES:
1. The optimal sampling point for the master is as close as possible to the end time of the 15 µs tRDV
period without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of
time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures
that a read will occur before the fastest 1-Wire device(s) release the line (tRELEASE = 0).
2. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 µs of this falling edge.
3. An additional reset or communication sequence cannot begin until the reset high time (tRSTH) has
expired.
4. The reset low time (tRSTL) should be restricted to a maximum of 960 µs, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
AC ELECTRICAL CHARACTERISTICS - OVERDRIVE 1-WIRE SPEED
2.8V ≤ VPUP ≤ 6.0V, -40°C ≤ TA ≤ +85°C
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
Time Slot
tSLOT
6
16
µs
Write 1 Low Time
tLOW1
1
2
µs
Write 0 Low Time
tLOW0
6
16
µs
Read Low Time
tLOWR
1
2
µs
Read Data Valid
tRDV
2
µs
9
Release Time
tRELEASE
0
1.5
4
µs
Read Data Setup
tSU
1
µs
4
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