DS3231SN View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
'DS3231SN' PDF : 19 Pages View PDF
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
START
CONDITION
1
2
6
7
8
9
ACK
Figure 2. I2C Data Transfer Overview
1
2
3–7
8
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERED
STOP
CONDITION
OR REPEATED
START
CONDITION
Figures 3 and 4 detail how data transfer is accom-
plished on the I2C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock puls-
es and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
The DS3231 can operate in the following two modes:
Slave receiver mode (DS3231 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
<SLAVE
<WORD
ADDRESS> ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)>
S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S = START
A = ACKNOWLEDGE
P = STOP
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D0H
Figure 3. Slave Receiver Mode (Write Mode)
<SLAVE
ADDRESS>
<DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S = START
A = ACKNOWLEDGE
P = STOP
A = NOT ACKNOWLEDGE
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY
A NOT ACKNOWLEDGE (A) SIGNAL
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D1H
Figure 4. Slave Transmitter Mode (Read Mode)
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3231 address,
which is 1101000, followed by the direction bit (R/W),
which is 0 for a write. After receiving and decoding
the slave address byte, the DS3231 outputs an
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