DS3232SN View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
'DS3232SN' PDF : 18 Pages View PDF
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
hours register is defined as the 12- or 24-hour mode
select bit. When high, 12-hour mode is selected. In 12-
hour mode, bit 5 is the AM/PM bit with logic-high being
PM. In 24-hour mode, bit 5 is the second 10-hour bit
(20–23 hours). The century bit (bit 7 of the month regis-
ter) is toggled when the years register overflows from
99 to 00.
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, sec-
ondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any START and when the register
pointer rolls over to zero. The time information is read
from these secondary registers, while the clock contin-
ues to run. This eliminates the need to reread the regis-
ters in case the main registers update during a read.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowl-
edge from the DS3232. Once the countdown chain is
reset, to avoid rollover issues the remaining time and
date registers must be written within 1 second. The 1Hz
square-wave output, if enabled, transitions high 500ms
after the seconds data transfer, provided the oscillator
is already running.
Alarms
The DS3232 contains two time-of-day/date alarms. Alarm
1 can be set by writing to registers 07h to 0Ah. Alarm 2
can be set by writing to registers 0Bh to 0Dh. The alarms
can be programmed (by the alarm enable and INTCN
bits of the control register) to activate the INT/SQW output
on an alarm match condition. Bit 7 of each of the time-of-
day/date alarm registers are mask bits (Table 2). When all
the mask bits for each alarm are logic 0, an alarm only
occurs when the values in the timekeeping registers
match the corresponding values stored in the time-of-
day/date alarm registers. The alarms can also be pro-
grammed to repeat every second, minute, hour, day, or
date. Table 2 shows the possible settings. Configurations
not listed in the table result in illogical operation.
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/DT is written to logic 1, the alarm will be the result of
a match with day of the week.
When the RTC register values match alarm register set-
tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition activates
the INT/SQW signal. The match is tested on the once-
per-second update of the time and date registers.
Table 2. Alarm Mask Bits
DY/DT
X
X
X
X
0
1
ALARM 1 REGISTER MASK BITS (BIT 7)
A1M4
A1M3
A1M2
A1M1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
ALARM RATE
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
DY/DT
X
X
X
0
1
ALARM 2 REGISTER MASK BITS (BIT 7)
A2M4
A2M3
A2M2
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
ALARM RATE
Alarm once per minute (00 seconds of every minute)
Alarm when minutes match
Alarm when hours and minutes match
Alarm when date, hours, and minutes match
Alarm when day, hours, and minutes match
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