External Memory Expansion Port (Port A)
A0–A17
AA0–AA3
WR
RD
100
107
101
102
114
119
103
118
TA
D0–D23
108
111
110
112
109
Data
Out
AA0469
Figure 3-10 SRAM Write Access
3.10.2 DRAM Timing
The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary selection only.
Final selection should be based on the timing provided in the following tables. As an example, the selection
guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM.
However, by using the information in the appropriate table, a designer may choose to evaluate whether
fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the
chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control
factors such as capacitive and resistive load to improve overall system performance.
3-16
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor