DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued)
20 MHz4
30 MHz4
No.
Characteristics
Symbol
Expression
Unit
Min Max Min Max
152 Last RD assertion to RAS deassertion tROH
1.5 × TC − 4.0
71.0
—
46.0
—
ns
153 RD assertion to data valid
tGA
154 RD deassertion to data not valid 6
tGZ
TC − 7.5
— 42.5 — 25.8 ns
0.0
—
0.0
—
ns
155 WR assertion to data active
0.75 × TC − 0.3 37.2
—
24.7
—
ns
156 WR deassertion to data high
impedance
0.25 × TC
— 12.5 —
8.3
ns
1 The number of wait states for Page mode access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 2 × TC for
read-after-read or write-after-write sequences).
4 Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 3-14.).
5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-19
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