External Memory Expansion Port (Port A)
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued)
66 MHz
80 MHz
No.
Characteristics3
Symbol Expression4
Unit
Min Max Min Max
164 CAS assertion to RAS deassertion
tRSH
3.25 × TC − 4.0 45.2
—
36.6
—
ns
165 RAS assertion to CAS deassertion
tCSH
4.75 × TC − 4.0 68.0
—
55.5
—
ns
166 CAS assertion pulse width
tCAS
2.25 × TC − 4.0 30.1
—
24.1
—
ns
167 RAS assertion to CAS assertion
tRCD
2.5 × TC ± 2
35.9
39.9
29.3
33.3
ns
168 RAS assertion to column address valid tRAD
1.75 × TC ± 2
24.5
28.5
19.9
23.9
ns
169 CAS deassertion to RAS assertion
tCRP
4.25 × TC − 4.0 59.8
—
49.1
—
ns
170 CAS deassertion pulse width
tCP
2.75 × TC − 4.0 37.7
—
30.4
—
ns
171 Row address valid to RAS assertion
tASR
3.25 × TC − 4.0 45.2
—
36.6
—
ns
172 RAS assertion to row address not valid tRAH
1.75 × TC − 4.0 22.5
—
17.9
—
ns
173 Column address valid to CAS
assertion
tASC
0.75 × TC − 4.0 7.4
—
5.4
—
ns
174 CAS assertion to column address not
tCAH
3.25 × TC − 4.0 45.2
—
36.6
—
ns
valid
175 RAS assertion to column address not
tAR
5.75 × TC − 4.0 83.1
—
67.9
—
ns
valid
176 Column address valid to RAS
deassertion
tRAL
4 × TC − 4.0
56.6
—
46.0
—
ns
177 WR deassertion to CAS assertion
178 CAS deassertion to WR5 assertion
179 RAS deassertion to WR5 assertion
180 CAS assertion to WR deassertion
181 RAS assertion to WR deassertion
182 WR assertion pulse width
183 WR assertion to RAS deassertion
184 WR assertion to CAS deassertion
185 Data valid to CAS assertion (write)
tRCS
2 × TC − 3.8
26.5
—
21.2
—
ns
tRCH
1.25 × TC − 3.7 15.2
—
11.9
—
ns
tRRH
0.25 × TC − 3.7 0.1
—
—
—
ns
0.25 × TC − 3.0 —
—
0.1
—
ns
tWCH
3 × TC − 4.2
41.3
—
33.3
—
ns
tWCR
5.5 × TC − 4.2 79.1
—
64.6
—
ns
tWP
8.5 × TC − 4.5 124.3
—
101.8
—
ns
tRWL
8.75 × TC − 4.3 128.3
—
105.1
—
ns
tCWL
7.75 × TC − 4.3 113.1
—
92.6
—
ns
tDS
4.75 × TC − 4.0 68.0
—
55.4
—
ns
3-30
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor