DSP56F802 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56F802' PDF : 40 Pages View PDF
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Typ
Max
Unit
Figure
Program time
Tprog*
20
–
–
us
Figure 3-4
Erase time
Terase*
20
–
–
ms
Figure 3-5
Mass erase time
Tme*
100
–
–
ms
Figure 3-6
Endurance1
ECYC
10,000 20,000
–
cycles
Data Retention1
DRET
10
30
–
years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
Tnvs*
–
5
–
us
Figure 3-4,
up time
Figure 3-5,
Figure 3-6
NVSTR hold time
Tnvh*
–
5
–
us
Figure 3-4,
Figure 3-5
NVSTR hold time (mass erase) Tnvh1*
–
100
–
us
Figure 3-6
NVSTR to program set up time
Tpgs*
–
10
–
us
Figure 3-4
Recovery time
Trcv*
–
1
–
us
Figure 3-4,
Figure 3-5,
Figure 3-6
Cumulative program
HV period2
Thv
–
3
–
ms
Figure 3-4
Program hold time3
Tpgh
–
–
–
Figure 3-4
Address/data set up time3
Tads
–
–
–
Figure 3-4
Address/data hold time3
Tadh
–
–
–
Figure 3-4
1. One Cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
56F802 Technical Data, Rev. 9
20
Freescale Semiconductor
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