dsPIC30F2011/2012/3012/3013
FIGURE 17-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
OST TIME-OUT
PWRT TIME-OUT
TOST
TPWRT
INTERNAL Reset
FIGURE 17-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
OST TIME-OUT
PWRT TIME-OUT
TOST
TPWRT
INTERNAL Reset
FIGURE 17-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
OST TIME-OUT
PWRT TIME-OUT
INTERNAL Reset
TOST
TPWRT
DS70139F-page 128
© 2008 Microchip Technology Inc.