DSPIC33FJ16GP304 View Datasheet(PDF) - Microchip Technology
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Description
MFG CO.
'DSPIC33FJ16GP304' PDF : 284 Pages View PDF
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
6.7 Configuration Mismatch Reset
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell
disturbances caused by ESD or other external events),
a configuration mismatch Reset occurs.
The Configuration Mismatch Flag bit (CM) in the
Reset Control register (RCON<9>) is set to indicate
the configuration mismatch Reset. Refer to
Section 10.0 “I/O Ports” for more information on the
configuration mismatch Reset.
Note:
The configuration mismatch feature and
associated reset flag is not available on all
devices.
6.8 Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag bit (IOPUWR) in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
6.8.1 ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.8.2
UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
6.8.3 SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to Section 19.6 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
6.9 Using the RCON Status Bits
The user application can read the Reset Control
register (RCON) after any device Reset to determine
the cause of the reset.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Table 6-3 provides a summary of the reset flag bit
operation.
TABLE 6-3: RESET FLAG BIT OPERATION
Flag Bit
Set by:
TRAPR (RCON<15>)
IOPWR (RCON<14>)
CM (RCON<9>)
Trap conflict event
Illegal opcode or uninitialized
W register access or Security Reset
Configuration Mismatch
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
MCLR Reset
RESET instruction
WDT time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
IDLE (RCON<2>)
PWRSAV #IDLE instruction
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
Note: All Reset flag bits can be set or cleared by user software.
Cleared by:
POR,BOR
POR,BOR
POR,BOR
POR
POR,BOR
PWRSAV instruction,
CLRWDT instruction, POR,BOR
POR,BOR
POR,BOR
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DS70290G-page 70
© 2011 Microchip Technology Inc.
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