DZPD6710VCB View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'DZPD6710VCB' PDF : 138 Pages View PDF
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
11.0 Timing Registers
The following information about the timing registers is important:
• All timing registers take effect immediately and should only be changed when the FIFO is
empty (see the FIFO Control register on “FIFO Control” on page 72).
• Selection of Timing 0 or Timing 1 register sets is controlled by I/O Window Control, bit 3
and/or bit 7 (see “I/O Window Control” on page 58).
11.1
Setup Timing 0–1
Register Name: Setup Timing 0–1
Index: 3Ah, 3Dh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Register Per: socket
Register Compatibility Type: 365
Bit 1
Bit 0
Setup Prescalar Select
Setup Multiplier Value
RW:00
RW:000001
There are two separate Setup Timing registers, each with identical fields. These registers are
located at the following indexes:
Index Setup Timing
3Ah Setup Timing 0
3Dh Setup Timing 1
The Setup Timing register for each timing set controls how long a PC Card cycle’s command (that
is, -OE, -WE, -IORD, -IOWR; see Table 2 on page 20) setup will be, in terms of the number of
internal clock cycles.
The overall command setup number of clocks S is programmed by selecting a 2-bit prescaling
value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a
multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command
setup timing length according to the following formula:
S = (Npres × Nval) + 1
The value of S, representing the number of internal clock cycles for command setup, is then
multiplied by the internal clock’s period to determine the command setup time (see “PC Card Bus
Timing Calculations” on page 109 for further discussion).
Bits 5:0 — Setup Multiplier Value
This field indicates an integer value Nval from 0 to 63; it is combined with a prescalar value (bits
7:6) to control the length of setup time before a command becomes active.
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Datasheet
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