EELXT905PC.C2 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'EELXT905PC.C2' PDF : 38 Pages View PDF
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
2.9
Loopback Functions
2.9.1
Internal Loopback
The LXT905 provides standard loopback mode as specified in the IEEE specification for the
twisted-pair port, as well as a forced internal loopback mode. Loopback mode operates in
conjunction with the transmit function. Data transmitted by the MAC is internally looped back
within the LXT905 from the TXD pin through the Manchester encoder/decoder to the RXD pin
and returned to the MAC.
Standard loopback mode is disabled when a data collision occurs, clearing the RXD circuit for the
TPI data. Standard loopback is also disabled during link fail, jabber, and full-duplex states.
Loopback is always enabled during forced internal loopback mode.
2.9.2
External Loopback/Full Duplex
The LXT905 also provides an external loopback test mode for system-level testing. When both
LEDC/FDE and LBK are Low, the LXT905 enables external loopback and full-duplex mode.
Internal loopback circuits, SQE, and collision detection are disabled. Refer to Table 3 for a
summary of loopback and duplex modes.
Table 3. Loopback Modes
Pin Settings
LBK
LEDC/
FDE
Mode Description
Low
Low
High
High
Low
High
Low
High
Disable internal loopback.
Enable external loopback test mode and full-duplex mode.
Standard loopback mode (default).
Data transmitted by the MAC is internally looped back and returned to the MAC except during
collision.
Standard loopback is disabled when a data collision occurs, clearing RXD for data on the
twisted-pair port.
Not Used.
Forced internal loopback.
Transmit data is looped back on the receive data bus and the twisted-pair port is ignored.
2.10
Link Integrity Test Function
Figure 7 on page 16 is a state diagram of the LXT905 Link Integrity test function. The link
integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity
testing is enabled when LI is tied High. When enabled, the receiver recognizes link integrity pulses
which are transmitted in the absence of receive traffic. If no serial data stream or link integrity
pulses are detected within 50~150 ms, the chip enters a link fail state and disables the transmit and
normal loopback functions. The LXT905 ignores any link integrity pulse with interval less than
2~7 ms. The LXT905 remains in the link fail state until it detects either a serial data packet or two
or more link integrity pulses.
Datasheet
15
Document #: 249271
Revision #: 002
Rev. Date: June 19, 2001
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