EI16C550 View Datasheet(PDF) - A1 PROs co., Ltd.

Part Name

Description

MFG CO.

EI16C550

FIFO UART

A1 PROs co., Ltd. 

1 2

Ei16C550

FIFO UART

Semiconductor, Inc.

The UART includes a programmable baud generator

which is capable of dividing the timing reference clock

input by divisors of 1 to (216-1), and producing a 16 x

clock to drive the receiver logic. Also included in the

UART is a complete MODEM control capability, and

processor interrupt system that may be software tai-

lored to the users requirement to minimize the com-

puting needed to handle the communications link.

BLOCK DIAGRAM

D7-D0

(1-8)

DATA

BUS

BUFFER

INTERNAL

DATA BUS

A0

A1

A2

CS0

CS1

CS2•

ADR

MR

DISTR

DISTR•

DOSTR

DOSTR•

DDIS

TXRDY•

XTAL1

XTAL2

RXRDY•

(28)

(27)

(26)

(12)

(13)

(14)

(25)

(35)

SELECT

(22)

AND

(21) CONTROL

(19)

LOGIC

(18)

(23)

(24)

(16)

(17)

(29)

POWER (40) 3.3, 5V

SUPPLY (20) GND

RECEIVER

BUFFER

REGISTER

LINE

CONTROL

REGISTER

DIVISOR

LATCH

(LS)

DIVISOR

LATCH

(MS

LINE

STATUS

REGISTER

FIFO

MODEM

CONTROL

REGISTER

MODEM

STATUS

REGISTER

INTERRUPT

ENABLE

REGISTER

INTERRUPT

ID

REGISTER

FIFO

CONTROL

REGISTER

RECEIVER

SHIFT

REGISTER

(10)

SIN

BAUD

GENERATOR

RECEIVER

TIMING

&

CONTROL

(15)

(9) RCLK

BAUDOUT

TRANSMITTER

TIMING

&

CONTROL

INTERRUPT

CONTROL

LOGIC

TRANSMITTER (11)

SHIFT

REGISTER

SOUT

MODEM

CONTROL

LOGIC

(32)

(36)

(33)

(37)

(38)

(39)

(34)

(31)

RTS•

CTS•

DTR•

DSR•

DCD•

RI•

OUT1•

OUT2•

(30) INTRPT

8

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