
Preliminary
EM83040B
LCD CONTROLLER
RAMEN
Ten RAM enable
RAMADS
RAMD(3:0)
RAMW
ADDRESS
A3 A2 A1
DATA
D1
Tdv
RAMR
A3=address (11:8) A2=address(7:0) A1=address(3:0)
D1= first nibble D2=second nibble D3=third nibble data
RAM disable
Tdd
D2
D3
Tdh
APPLICATION CIRCUIT
(1) C32 x S48
Fig .13 LCD RAM read mode
NC
VDD
LOAD
GND
VOUT
VDD
VDD
VDD
MAIN
VSS4
VSS3
M1
CB
M0
CA
EN
VSS2+
RAMEN
VSS2-
NC
RAMADS VREG
RAMW
V1
RAMR
V2
V3
RAMD(3:0)
V4
V5
Fig .14
* This specification are subject to be changed without notice.
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