EMC6D102-CZC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
EMC6D102-CZC
SMSC -> Microchip
'EMC6D102-CZC' PDF : 86 Pages View PDF
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
Reg
Addr
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
Read/
Write
R
R
R
R
R/W
R
R/W
R
R
R/W
R/W
R/W
R/W
R/W
95h R/W
96h R/W
97h R/W
98h R/W
99-FEh R
FFh
R
Table 7.1 Register Summary (continued)
Reg Name
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
Reserved
Tach1 Option
Tach2 Option
Tach3 Option
Tach4 Option
PWM1 Option
PWM2 Option
PWM3 Option
SMSC Test Register
SMSC Test Register
Reserved
SMSC Test Register
Bit 7
MSb
Bit 6
Bit 5
V50.3 V50.2 V50.1
VCC.3 VCC.2 VCC.1
TST7 TST6 TST5
RES TST6 TST5
RES TST6 TST5
RES RES RES
RES RES RES
TST7 TST6 TST5
RES RES RES
STCH2 STCH1 STCH0
STCH2 STCH1 STCH0
STCH2 STCH1 STCH0
STCH2 STCH1 STCH0
RES RES OPP
Note 7.6 Note 7.6
RES RES OPP
Note 7.6 Note 7.6
RES RES OPP
Note 7.6 Note 7.6
TST7 TST 6 TST 5
TST7 TST 6 TST 5
RES RES RES
TST7 TST 6 TST 5
Bit 4
V50.0
VCC.0
TST4
TST4
TST4
TST4
TST4
TST4
RES
3EDG
3EDG
3EDG
3EDG
GRD1
GRD1
GRD1
TST 4
TST 4
RES
TST 4
Bit 3
V25.3
VCP.3
TST3
TST3
TST3
TST3
TST3
TST3
RES
MODE
MODE
MODE
MODE
GRD0
GRD0
GRD0
TST3
TST3
RES
TST3
Bit 2
V25.2
VCP.2
TST2
TST2
TST2
TST2
TST2
TST2
RES
EDG1
EDG1
EDG1
EDG1
SZEN
SZEN
SZEN
TST2
TST2
RES
TST2
Bit 1
Bit 0
LSb
V25.1 V25.0
VCP.1 VCP.0
TST1 TST0
TST1 TST0
TST1 TST0
TST1 TST0
TST1 TST0
TST1 TST0
RES RES
EDG0 SLOW
EDG0 SLOW
EDG0 SLOW
EDG0 SLOW
UPDT1 UPDT0
UPDT1 UPDT0
UPDT1 UPDT0
TST1
TST1
RES
TST1
TST0
TST0
RES
TST0
Default
Value
N/A
N/A
N/A
4Dh
4Dh
09h
09h
N/A
00h
CCh
CCh
CCh
CCh
0Ch
0Ch
0Ch
5Ah
F1h
00h
N/A
Lock
No
No
No
No
Yes
No
Yes
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
No
No
Start
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted
results.
Note 7.1
The PWMx Current Duty Cycle Registers are only writable when the associated fan is in
manual mode. In this case, the register is writable when the start bit is set, but not when
the lock bit is set.
Note 7.2 The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The
OVRID bit is always writable, both when the start bit is set and when the lock bit is set.
Note 7.3 The Interrupt status registers are cleared on a read if no events are active
Note 7.4 The INTEN bit in register 7Ch is always writable, both when the start bit is set and when
the lock bit is set.
Note 7.5
In Shutdown Mode (LPMD=1 & START=0) all the H/W Monitoring registers/bits are not
accessible except for the following: Bits[2:0] in the Special Function Register (SFTR) at
offset 7Ch and Bits[7:0] in the Configuration register at offset 7Fh.
Note 7.6 These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the
hardware.
Note 7.7 SMSC bits may be read/write bits. Writing these bits to a value other than the default value
may cause unwanted results
7.1
Undefined Registers
The registers shown in the table above are the defined registers in the part. Any reads to undefined
registers always return 00h. Writes to undefined registers have no effect and do not return an error.
SMSC EMC6D102
47
DATASHEET
Revision 0.4 (04-05-05)
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