EMC6D102-CZC-TR View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
EMC6D102-CZC-TR
SMSC -> Microchip
'EMC6D102-CZC-TR' PDF : 86 Pages View PDF
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
Diode 2 Limit Error) in addition to the diode fault bit. Disabling the enable bit for the diode will clear
both the fault bit and the error bit for that diode (see Note below).
This register is read only – a write to this register has no effect.
Note:
Clearing the individual enable bits:
1. An interrupt status bit will never change from a 0 to a 1 when the corresponding individual interrupt
enable bit is cleared (set to 0), regardless of whether the limits are violated during a measurement.
2. If the individual enable bit is cleared while the associated status bit is 1, the status bit will be
cleared when the associated reading register is updated. The reading registers only get updated
when the START bit is set to ‘1’. If the enable bit is cleared when the START bit is 0, the associated
interrupt status bit will not be cleared until the start bit is set to 1 and the associated reading register
is updated.
BIT
NAME
R/W DEFAULT
DESCRIPTION
0 +12v_Error R
1
Reserved
R
2
TACH1
R
Slow/Stalled
3
TACH2
R
Slow/Stalled
4
TACH3
R
Slow/Stalled
5
TACH4
R
Slow/Stalled
6
Remote
R
Diode 1 Fault
7
Remote
R
Diode 2 Fault
0 The EMC6D102 automatically sets this bit to 1 when the 12V input
voltage is less than or equal to the limit set in the 12V Low Limit register
or greater than the limit set in the 12V High Limit register.
0 Reserved
0 The EMC6D102 automatically sets this bit to 1 when the TACH1 input
reading is above the value set in the Tach1 Minimum MSB and LSB
registers.
0 The EMC6D102 automatically sets this bit to 1 when the TACH2 input
reading is above the value set in the Tach2 Minimum MSB and LSB
registers.
0 The EMC6D102 automatically sets this bit to 1 when the TACH3 input
reading is above the value set in the Tach3 Minimum MSB and LSB
registers.
0 The EMC6D102 automatically sets this bit to 1 when the TACH4 input
reading is above the value set in the Tach4 Minimum MSB and LSB
registers.
0 The EMC6D102 automatically sets this bit to 1 when there is either a
short or open circuit fault on the Remote1+ or Remote1- thermal diode
input pins as defined in the section Diode Fault on page 22.
Note: If the START bit is set and a fault condition exists, the Remote
Diode 1 reading register will be forced to 80h.
0 The EMC6D102 automatically sets this bit to 1 when there is either a
short or open circuit fault on the Remote2+ or Remote2- thermal diode
input pins as defined in the section Diode Fault on page 22.
Note: If the START bit is set and a fault condition exists, the Remote
Diode 2 reading register will be forced to 80h.
7.2.12 Register 43h: VID
Register
Address
43h
Read/
Write
R
Register Name
VID0-4
Bit 7
(MSb)
RES
Bit 6
RES
Bit 5
RES
Bit 4
VID4
Bit 3
VID3
Bit 2 Bit 1
VID2 VID1
Bit 0
(LSb)
VID0
Default
Value
N/A
The VID register contains the values of EMC6D102 VID0-VID4 input pins. This register indicates the
status of the VID lines that interconnect the processor to the Voltage Regulator Module (VRM).
Software uses the information in this register to determine the voltage that the processor is designed
to operate at. With this information, software can then dynamically determine the correct values to
place in the Vccp Low Limit and Vccp High Limit registers.
Revision 0.4 (04-05-05)
56
DATASHEET
SMSC EMC6D102
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