EMIF01-10018W5 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EMIF01-10018W5' PDF : 10 Pages View PDF
EMIF01-10018W5
ESD PROTECTION
In addition to its filtering function, the EMIF01-10018W5 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at :
VCL = VBR + Rd.IPP
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and
then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output
voltage very low at the Vout level.
Fig. A3: ESD clamping behavior.
Rg
R
ESD
Surge
Vg
Rd
Rd
Vin
Vout
Vbr
Vbr
Rload
S1
S2
EMIF01-10018W5
Device to be protected
To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical
resistance value Rd. By taking into account these following hypothesis : R>>Rd, RG>>Rd and Rload>>Rd, it gives these
formulas:
Vin
=
Rg.Vbr+Rd.Vg
Rg
Vout
=
R.Vbr+Rd.Vin
R
The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV, Rg=330Ω) and VBR=7V
(typ.) give:
Vin = 31.2 V
Vout = 7.3 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this
approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at
the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.
LATCH-UP PHENOMENA
The early ageing and destruction of IC’s is often due to latch-up phenomena which mainly induced by dV/dt. Thanks to
its RC structure, the EMIF01-10018W5 provides a high immunity to latch-up by integration of fast edges. (Please see the
response of EMIF01-10018W5 to a 3 ns edge on Fig. A9)
The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD protection :
- almost no influence of the parasitic inductances on Vout stage
- Vout clamping voltage very close to Vbr
Fig. A4: Measurement conditions
ESD
SURGE
TEST BOARD
16kV
Air
Vin
Discharge
Vout
4/10
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