EMIF03-SIM01 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EMIF03-SIM01' PDF : 11 Pages View PDF
Fig. A2: Measurements conditions
50 Ω
Vg
TEST BOARD
EMI03
SIM01
EMIF03-SIM01
50 Ω
ESD PROTECTION
In addition with the filtering the EMIF03-SIM01 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at:
Vcl = Vbr + Rd ⋅ Ipp
This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by the
first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R.
Such a configuration makes the output voltage very low at the Vout level.
Fig. A3: ESD clamping behavior
Rg
S1 R = 100Ω or 47Ω S2
Vg
ESD Surge
Rd
VBR
Vin
Vout
Rd
VBR
EMIF03-SIM01
R load
Device
to be
protected
5/11
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