EP7212-CV-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
EP7212-CV-A
Cirrus Logic
'EP7212-CV-A' PDF : 136 Pages View PDF
EP7212
tus flag CRXFE is set and CTXFF is cleared so that
the FIFOs appear empty. Additionally, if the
CDENTX bit is low, the PCMOUT output is dis-
abled. Asserting either of the two enable bits causes
the sync and interrupt generation logic to become
active; otherwise they are disabled to conserve
power.
Data is loaded into the transmit FIFO by writing to
the CODR register. At the beginning of a transmit
cycle, this data is loaded into a shift/load register.
Just prior to the byte being transferred out, PCM-
SYNC goes high for one PCMCLK cycle. Then the
data is shifted out serially to PCMOUT, MSB first,
(with the MSB valid at the same time PCMSYNC
is asserted). Data is shifted on the rising edge of the
PCMCLK output.
Receiving of data is performed by taking data in se-
rially through PCMIN, again MSB first, shifting it
through the shift/load register and loading the com-
plete byte into the receive FIFO. If there is no data
available in the transmit FIFO, then a zero will be
loaded into the shift/load register. Input data is
sampled on the falling edge of PCMCLK. Data is
read from the CODR register.
3.13.2 Digital Audio Interface
The DAI interface provides a high quality digital
audio connection to DAI compatible audio devices.
The DAI is a subset of I2S audio format that is sup-
ported by a number of manufacturers.
The DAI interface produces one 128-bit frame at
the audio sample frequency using a bit clock and
frame sync signal. Digital audio data is transferred,
full duplex, via separate transmit and receive data
lines. The bit clock frequency is either fixed at
9.216 MHz or set via an externally supplied MCLK
signal.
The DAI interface contains separate transmit and
receive FIFO’s. The transmit FIFO’s are 8 audio
CDENRX
CDENTX
CSINT
1 ms
1 ms
1 ms
Figure 6. Codec Interrupt Timing
40
DS474PP1
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