Revision History
EP7312
High-Performance, Low-Power System on Chip
Revision
PP5
F1
F2
Date
JAN 2004
AUG 2005
MAR 2011
Changes
Preliminary release. Updated SDRAM timing.
Updated ordering information. Added MSL data.
Removed all lead-containing device ordering information. Removed 204-pin
TFBGA package option.
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
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