EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory Turnaround Cycle
Parameter
Symbol
Min
CSnX deassert to CSnY assert time
tBTcyc
-
Note: X and Y represent any two chip select numbers.
Typ
tHCLK × (IDCY+1)
Max
-
Unit
ns
AD
CSnX0
CSnY1
WRn
RDn
DQMn
DA
WAIT
tBTcyc
Figure 15. Static Memory Turnaround Cycle Timing Measurement
28
©Copyright 2004 Cirrus Logic (All Rights Reserved)
DS667PP3