EVAL-AD1839EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD1839EB' PDF : 24 Pages View PDF
AD1839
Pin Name
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
DLRCLK (I)/AUXLRCLK(I/O)
DBCLK (I)/AUXBCLK(I/O)
DAUXDATA(O)
Table II. Pin Function Changes in Auxiliary Mode
I2S Mode
I2S Data Out, Internal ADC
I2S Data In, Internal DAC1
I2S Data In, Internal DAC2
I2S Data In, Internal DAC3
Not Connected
LRCLK for ADC
BCLK for ADC
LRCLK In/Out Internal DACs
BCLK In/Out Internal DACs
Not Connected
Aux Mode
TDM Data Out to SHARC
TDM Data In from SHARC
AUX-I2S Data In 1 (from Ext. ADC)
AUX-I2S Data In 2 (from Ext. ADC)
AUX-I2S Data In 3 (from Ext. ADC)
TDM Frame Sync Out to SHARC (FSTDM)
TDM BCLK Out to SHARC
AUX LRCLK In/Out. Driven by Ext. LRCLK
from ADC in slave mode. In master mode,
driven by MCLK/512.
AUX BCLK In/Out. Driven by Ext. BCLK from
ADC in slave mode. In master mode, driven by
MCLK/8.
AUX-I2S Data Out (to Ext. DAC)
FSTDM
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
MSB TDM
1ST
CH
MSB TDM
8TH
CH
INTERNAL
ADC L1
32
MSB TDM
1ST
CH
AUX_ADC L2 AUX_ADC L3 AUX_ADC L4
INTERNAL
ADC R1
AUX_ADC R2 AUX_ADC R3 AUX_ADC R4
MSB TDM
8TH
CH
INTERNAL
DAC L1
32
INTERNAL
DAC L2
INTERNAL
DAC L3
AUX DAC L4
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
AUX DAC R4
AUX
LRCLK I2S
(FROM AUX ADC 1)
AUX
BCLK I2S
(FROM AUX ADC 1)
AAUXDATA1 (IN)
(FROM AUX ADC 1)
AAUXDATA2 (IN)
(FROM AUX ADC 2)
LEFT
I2S— MSB LEFT
I2S— MSB LEFT
RIGHT
I2S— MSB RIGHT
I2S— MSB RIGHT
AAUXDATA3 (IN)
(FROM AUX ADC 3)
I2S— MSB LEFT
AUX BCLK FREQUENCY IS 64 ؋ FRAME RATE; TDM BCLK FREQUENCY IS 256 ؋ FRAME RATE.
Figure 11. Aux Mode Timing
I2S— MSB RIGHT
–16–
REV. B
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