EVAL-AD1938AZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD1938AZ' PDF : 32 Pages View PDF
AD1928
DIGITAL FILTERS
Table 6.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes, typ @ 48 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
Factor
0.4375 fS
0.5 fS
0.5625 fS
22.9844/fS
0.4535 fS
0.3646 fS
0.3646 fS
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
25/fS
11/fS
8/fS
Min Typ
Max
Unit
21
kHz
±0.015
dB
24
kHz
27
kHz
79
dB
479
μs
22
35
70
24
48
96
26
61
122
70
70
70
521
115
42
kHz
kHz
kHz
±0.01 dB
±0.05 dB
±0.1
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
TIMING SPECIFICATIONS
−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK) AND
RESET
tMH
Condition
MCLK duty cycle
fMCLK
tPDR
tPDRR
PLL
Lock Time
256 fS VCO Clock Output Duty Cycle
MCLK frequency
RST low
RST recovery
MCLK and LR
clock input
MCLKO/XO pin
Comments
DAC/ADC clock source = PLL clock @ 256 fS,
384 fS, 512 fS, and 768 fS
DAC/ADC clock source = direct MCLK @ 512 fS
(bypass on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
Reset to active output
Min Max Unit
40
60
%
40
60
%
6.9 13.8
27.6
15
4096
MHz
MHz
ns
tMCLK
10 ms
40
60
%
Rev. 0 | Page 6 of 32
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