EVAL-AD1940EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD1940EB' PDF : 32 Pages View PDF
AD1940/AD1941
RAMS AND REGISTERS
Table 17. Control Port Addresses
SPI/ I2C Subaddress
0–1023 (0x0000–0x03FF)
1024–2559 (0x0400–0x09FF)
2560–2623 (0x0A00–0x0A3F)
2624–2628 (0x0A40–0x0A44)
2629–2633 (0x0A45–0x0A49)
2634–2639 (0x0A4A–0x0A4F)
2640–2641 (0x0A50–0x0A51)
2642 (0x0A52)
2643 (0x0A53)
2644 (0x0A54)
2645 (0x0A55)
2646 (0x0A56)
Register Name
Parameter RAM
Program RAM
Target/Slew RAM
Parameter RAM Data Safeload Registers 0–4
Parameter RAM Indirect Address Safeload Registers 0–4
Data Capture Registers 0–5 (Control Port Readback)
Data Capture Registers (Digital Output)
DSP Core Control Register
RAM Configuration Register
Serial Output Control Register 1 (Channels 0–7)
Serial Output Control Register 2 (Channels 8–15)
Serial Input Control Register
Read/Write Word Length
Write: 4 bytes, read: 4 bytes
Write: 5 bytes, read: 5 bytes
Write: 5 bytes, read: n/a
Write: 5 bytes, read: n/a
Write: 2 bytes, read: n/a
Write: 2 bytes, read: 3 bytes
Write: 2 bytes, read: n/a
Write: 2 bytes, read: 2 bytes
Write: 1 byte, read: 1 byte
Write: 2 bytes, read: 2 bytes
Write: 2 bytes, read: 2 bytes
Write: 1 byte, read: 1 byte
Table 18. RAM Read/Write Modes
Memory
Subaddress
Size
Range
Parameter RAM
1024 × 28 0–1023
(0x0000–0x03FF)
Program RAM
1536 × 40 1024–2559
(0x0400–0x09FF)
Target/Slew RAM 64 × 34
2560–2623
(0x0A00–0x0A3F)
Read
Yes
Yes
No
Write
Yes
Yes
Yes (via
safeload)
Burst Mode
Available
Yes
Write Modes
Direct write1 or safeload write
Yes
Direct write1
Yes2
Safeload write
1 DSP core should be shut down first to avoid clicks/pops.
2 The target/slew RAMs need to be written through the safeload registers. Safeload writes may be done in either single write mode or burst mode.
CONTROL PORT ADDRESSING
Table 17 shows the addressing of the AD1940/AD1941’s RAM
and register spaces. The address space encompasses a set of
registers and three RAMs: one each for holding signal
processing parameters, holding the program instructions, and
ramping parameter values. The program and parameter RAMs
are initialized on power-up from on-board boot ROMs.
Table 18 shows the sizes and available writing modes of the
parameter, program, and target/slew RAMs.
PARAMETER RAM CONTENTS
The parameter RAM is 28 bits wide and occupies Addresses 0 to
1023. The parameter RAM is initialized to all 0s on power-up.
The data format of the parameter RAM is twos complement
5.23. This means that the coefficients may range from +16.0
(minus 1 LSB) to –16.0, with 1.0 represented by the binary word
0000 1000 0000 0000 0000 0000 0000.
Options for Parameter Updates
The parameter RAM can be written and read using one of the
two following methods.
1. Direct Read/Write. This method allows direct access to the
program and parameter RAMs. This mode of operation is
normally used during a complete new load of the RAMs,
using burst mode addressing. The clear register bit in the
core control register should be set to 0 using this mode to
avoid any clicks or pops in the outputs. Note that it is also
possible to use this mode during live program execution,
but since there is no handshaking between the core and the
control port, the parameter RAM is unavailable to the DSP
core during control writes, resulting in clicks and pops in
the audio stream.
2. Safeload Write. Up to five safeload registers can be loaded
with parameter RAM address/data. The data is then
transferred to the requested address when the RAM is not
busy. This method can be used for dynamic updates while
live program material is playing through the AD1940/
AD1941. For example, a complete update of one biquad
section can occur in one audio frame, while the RAM is
not busy. This method is not available for writing to the
program RAM or control registers.
The following sections discuss these two options in more detail.
Rev. A | Page 19 of 36
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