EVAL-AD421EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD421EB' PDF : 14 Pages View PDF
AD421
TIMING CHARACTERISTICS1, 2, 3 (VCC = +3 V to +5 V, TA = TMIN to TMAX unless otherwise noted)
Parameter
(B Versions)
Units
Conditions/Comments
tCK
100
tCL
50
tCH
50
tDW
30
tDS
30
tDH
0
tLD
50
tLL
50
tLH
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
NOTES
1Guaranteed by characterization at initial product release, not production tested.
2See Figures 1 and 2.
3All input signals are specified with tr = tf = 5 ns (10% to 90% of V CC ) and timed from a voltage level of (VIN + VIL )/2; tr and tf should not exceed 1 µs on any digital
input.
Specifications subject to change without notice.
CLOCK
DATA
WORD "N"
1 0 11 0 0 1 0 0 1 1 1 0 0 11
WORD "N +1"
1 00 1
LATCH
Figure 1. Serial Interface Waveforms (Normal Data Load)
CLOCK
DATA
LATCH
tCL
tDS
tCK
tCH
tDH
tDW
tLD
tLL
tLH
Figure 2. Serial Interface Timing Diagram
REV. C
–3–
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