EVAL-AD5111SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5111SDZ
Analog Devices
'EVAL-AD5111SDZ' PDF : 24 Pages View PDF
Data Sheet
POWER-UP SEQUENCE
Because of the ESD protection diodes that limit the voltage
compliance at the A, B, and W terminals (see Figure 45), it is
important to power on VDD before applying any voltage to the
A, B, and W terminals. Otherwise, the diodes are forward-
biased such that VDD is powered on unintentionally and can
affect other parts of the circuit. Similarly, VDD should be
powered down last. The ideal power-on sequence is in the
following order: GND, VDD, and VA/VB/VW. The order of
powering VA, VB, VW and the digital inputs is not important as
long as they are powered on after VDD.
VDD
A
W
B
GND
Figure 45. Maximum Terminal Voltages Set by VDD and GND
AD5111/AD5113/AD5115
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 46 illustrates the basic supply bypassing configuration
for the AD5111/AD5113/AD5115.
VDD + C2
10µF
C1
0.1µF
AD5111/
AD5113/
AD5115
VDD
GND
AGND
Figure 46. Power Supply Bypassing
Rev. B | Page 21 of 24
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