EVAL-AD5142DBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5142DBZ
Analog Devices
'EVAL-AD5142DBZ' PDF : 32 Pages View PDF
Data Sheet
AD5122/AD5142
INDEP 1
16 SYNC
RESET 2
15 SDO
GND 3
A1 4
W1 5
B1 6
VSS 7
AD5122/
AD5142
TOP VIEW
(Not to Scale)
14 SDI
13 SCLK
12 VLOGIC
11 VDD
10 B2
A2 8
9 W2
Figure 7. 16-Lead TSSOP, SPI Interface Pin Configuration
Table 9. 16-Lead TSSOP, SPI Interface Pin Function Descriptions
Pin No. Mnemonic
Description
1
INDEP
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated
memory location. If INDEP is enabled, it cannot be disabled by software.
2
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is
not used, tie RESET to VLOGIC.
3
GND
Ground Pin, Logic Ground Reference.
4
A1
5
W1
6
B1
7
VSS
8
A2
9
W2
10
B2
11
VDD
12
VLOGIC
13
SCLK
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
14
SDI
Serial Data Input.
15
SDO
Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.
16
SYNC
Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.
Rev. C | Page 13 of 32
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