AD5124/AD5144/AD5144A
Table 21. Address Bits
A3 A2 A1 A0
1
X1
X1
X1
0000
0100
0001
0101
0010
0110
0011
0111
1 X = don’t care.
Potentiometer Mode
Input Register
RDAC Register
All channels
All channels
RDAC1
RDAC1
Not applicable
Not applicable
RDAC2
RDAC2
Not applicable
Not applicable
RDAC3
RDAC3
Not applicable
Not applicable
RDAC4
RDAC4
Not applicable
Not applicable
Linear Gain Setting Mode
Input Register
RDAC Register
All channels
All channels
RWB1
RWB1
RAW1
RAW1
RWB2
RWB2
RAW2
RAW2
RWB3
RWB3
RAW3
RWB4
RAW3
RWB4
RAW4
RAW4
Table 22. Control Register Bit Descriptions
Bit Name
Description
D0
RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
D1
EEPROM program enable
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
D2
Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
D3
Burst mode (I2C only)
0 = disabled (default)
1 = enabled (no disable after stop or repeat start condition)
Data Sheet
Stored RDAC
Memory
Not applicable
RDAC1
Not applicable
RDAC2
Not applicable
RDAC3
Not applicable
RDAC4
Not applicable
Rev. C | Page 30 of 36