EVAL-AD5324DBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5324DBZ
Analog Devices
'EVAL-AD5324DBZ' PDF : 24 Pages View PDF
AD5305/AD5315/AD5325
SCL
SDA
0
START
COND
BY
MASTER
0
0
11
0
A0
R/W
X
X
ADDRESS BYTE
ACK MSB
BY
AD53x5
POINTER BYTE
LSB
ACK
BY
AD53x5
SCL
SDA
0
REPEATED
START
COND
BY
MASTER
0
0
11
ADDRESS BYTE
0
A0 R/W
MSB
ACK
BY
AD53x5
DATA BYTE
LSB
ACK
BY
MASTER
SCL
SDA
MSB
LEAST SIGNIFICANT DATA BYTE
LSB
NO
ACK
BY
MASTER
STOP
COND
BY
MASTER
NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s.
Figure 34. Readback Sequence
DOUBLE-BUFFERED INTERFACE
The AD5305/AD5315/AD5325 DACs have double-buffered
interfaces consisting of two banks of registers—input registers
and DAC registers. The input register is directly connected to the
input shift register and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The DAC
register contains the digital code used by the resistor string.
Access to the DAC register is controlled by the LDAC bit. When
the LDAC bit is set high, the DAC register is latched and,
therefore, the input register can change state without affecting
the contents of the DAC register. However, when the LDAC bit
is set low, the DAC register becomes transparent and the
contents of the input register are transferred to it.
This is useful if the user requires simultaneous updating of all
DAC outputs. The user can write to three of the input registers
individually and then, by setting the LDAC bit low when
writing to the remaining DAC input register, all outputs update
simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5305/AD5315/
AD5325, the part updates the DAC register only if the input
register has been changed since the last time the DAC register
was updated, thereby removing unnecessary digital crosstalk.
POWER-DOWN MODES
The AD5305/AD5315/AD5325 have very low power consumption,
dissipating typically 1.5 mW with a 3 V supply and 3 mW with
a 5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 15 and Bit 14
(PD1 and PD0) of the data byte. Table 8 shows how the state of
the bits corresponds to the mode of operation of the DAC.
Table 8. PD1/PD0 Operating Modes
PD1 PD0 Operating Mode
0
0
Normal Operation
0
1
Power-Down (1 kΩ load to GND)
1
0
Power-Down (100 kΩ load to GND)
1
1
Power-Down (three-state output)
Rev. G | Page 18 of 24
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