EVAL-AD5324DBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5324DBZ
Analog Devices
'EVAL-AD5324DBZ' PDF : 24 Pages View PDF
AD5305/AD5315/AD5325
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2, 3
Output Voltage Settling Time
AD5305
AD5315
AD5325
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A, B Version1
Min Typ Max Unit Conditions/Comments
VREF = VDD = 5 V
6
8
μs
¼ scale to ¾ scale change (0×40 to 0×C0)
7
9
μs
¼ scale to ¾ scale change (0×100 to 0×300)
8
10
μs
¼ scale to ¾ scale change (0×400 to 0×C00)
0.7
V/μs
12
nV-s 1 LSB change around major carry
1
nV-s
1
nV-s
3
nV-s
200
kHz VREF = 2 V ± 0.1 V p-p
−70
dB
VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization, not production tested.
3 See the Terminology section.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
fSCL
t1
t2
t3
t4
t5
t6 3
t7
t8
t9
t10
t11
CB4
Limit at TMIN, TMAX (A, B Version)
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1 CB4
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Conditions/Comments
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus-free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Rev. G | Page 5 of 24
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