EVAL-AD5405EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5405EB
Analog Devices
'EVAL-AD5405EB' PDF : 24 Pages View PDF
AD5405
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
t14
t15
t16
t17
Data Readback Mode
t10
t11
t12
t13
Update Rate
Limit at TMIN, TMAX
0
0
10
10
0
6
0
5
7
10
12
10
10
0
0
5
35
5
10
21.3
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
Conditions/Comments
R/W-to-CS setup time
R/W-to-CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
CS rising-to-LDAC falling time
LDAC pulse width
CS rising-to-LDAC rising time
LDAC falling-to-CS rising time
Address setup time
Address hold time
Data access time
Bus relinquish time
Consists of CS min high time, CS low time, and output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
R/W
CS
DACA/DACB
DATA
LDAC1
LDAC2
t1
t2
t8
t9
t3
t4
t5
t10
t2
t11
t6
t7
DATA VALID
t17
t12
t13
DATA VALID
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Timing Diagram
t15
t16
200μA
IOL
TO
OUTPUT
PIN
CL
50pF
200μA
IOH
VOH (MIN) + VOL (MAX)
2
Figure 3. Load Circuit for Data Timing Specifications
Rev. B | Page 5 of 24
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