EVAL-AD5429EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5429EB
Analog Devices
'EVAL-AD5429EB' PDF : 32 Pages View PDF
AD5429/AD5439/AD5449
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 39 shows the DACs operating in voltage-switching mode.
The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is
connected to AGND, and the output voltage is available at the
VREF terminal. In this configuration, a positive reference voltage
results in a positive output voltage, making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance). Therefore, an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
Note that VIN is limited to low voltages, because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and this degrades
the integral linearity of the DAC. Also, VIN must not go negative
by more than 0.3 V or an internal diode turns on, exceeding the
maximum ratings of the device. In this type of application, the
DAC’s full range of multiplying capability is lost.
VDD
RFB VDD
VIN
IOUT1
IOUT2
VREF
GND
POSITIVE OUTPUT VOLTAGE
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and −2.5 V, respectively, as shown in Figure 40.
R1
R2
VOUT
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 39. Single-Supply Voltage-Switching Mode
VDD = +5V
ADR03
VOUT VIN
GND
+5V
–2.5V
1/2 AD8552
–5V
VREF
VDD
RFB
8-/10-/12-BIT
DAC
IOUT1
IOUT2
GND
C1
VOUT = 0V TO +2.5V
1/2 AD8552
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 40. Positive Voltage Output with Minimum Components
Rev. 0 | Page 17 of 32
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