EVAL-AD5429EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5429EB
Analog Devices
'EVAL-AD5429EB' PDF : 32 Pages View PDF
AD5429/AD5439/AD5449
Software LDAC Function
Load and update mode can also function as a software update
function, irrespective of the voltage level on the LDAC pin.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to this family of DACs is via a serial
bus that uses standard protocol compatible with microcon-
trollers and DSP processors. The communications channel is
a 3-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5429/AD5439/AD5449
require a 16-bit word with the default being data valid on the
falling edge of SCLK, but this is changeable via the control bits
in the data-word.
ADSP-21xx to AD5429/AD5439/AD5449 Interface
The ADSP-21xx family of DSPs is easily interfaced to this
family of DACs without the need for extra glue logic. Figure 47
is an example of an SPI interface between the DAC and the
ADSP-2191M. SCK of the DSP drives the serial data line, DIN.
SYNC is driven from one of the port lines, in this case SPIxSEL.
ADSP-2191*
SPIxSEL
MOSI
SCK
AD5429/AD5439/
AD5449*
SYNC
SDIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. ADSP-2191 SPI to AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 48. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP’s serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
ADSP-2101/
ADSP-2103/
ADSP-2191* TFS
DT
SCLK
AD5429/AD5439/
AD5449*
SYNC
SDIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to
AD5429/AD5439/AD5449 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface
expects a t4 SYNC falling edge to SCLK falling edge setup time)
of 13 ns minimum. See the ADSP-21xx User Manual for details
on clock and frame sync frequencies for the SPORT register.
Table 12 shows how the SPORT control register must be set up.
Table 12.
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
Setting
1
1
00
1
1
1
1111
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
80C51/80L51 to AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 49. TxD of the 80C51/80L51drives SCLK of the
DAC serial interface, while RxD drives the serial data line, DIN.
P1.1 is a bit-programmable pin on the serial port and is used to
drive SYNC. When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RXD is clocked out of
the microcontroller on the rising edge of TXD and is valid on
the falling edge. As a result, no glue logic is required between
the DAC and microcontroller interface. P1.1 is taken high
following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
into account.
80C51*
TxD
RxD
P1.1
AD5429/AD5439/
AD5449*
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 49. 80C51/80L51 to AD5429/AD5439/AD5449 Interface
Rev. 0 | Page 22 of 32
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