4.0
TA = 25°C
3.5
3.0
2.5
2.0
1.5
VDD = 5V
1.0
0.5
0
VDD = 3V
0
1
2
3
4
5
6
VLOGIC (V)
Figure 24. Supply Current vs. Logic Input Voltage
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
VOUT = 909mV/DIV
1
TIME BASE = 4μs/DIV
Figure 25. Full-Scale Settling Time
VDD = VREF = 5V
TA = 25°C
VDD
1
2
VOUT
MAX(C2)*
420.0mV
CH1 2.0V
CH2 500mV
M100μs 125MS/s
A CH1 1.28V
Figure 26. Power-On Reset to 0 V
8.0ns/pt
VDD
1
AD5666
VDD = VREF = 5V
TA = 25°C
2
VOUT
CH1 2.0V CH2 1.0V
M100μs 125MS/s 8.0ns/pt
A CH1 1.28V
Figure 27. Power-On Reset to Midscale
SYNC
1
SLCK
3
VOUT
VDD = 5V
2
CH1 5.0V CH2 500mV M400ns
CH3 5.0V
A CH1 1.4V
Figure 28. Exiting Power-Down to Midscale
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
2.489
2.488
2.487
2.486
2.485
0
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
GLITCH IMPULSE = 3.55nV-s
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
64 128 192 256 320 384 448 512
SAMPLE
Figure 29. Digital-to-Analog Glitch Impulse
Rev. D | Page 15 of 28