EVAL-AD5666EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5666EBZ' PDF : 28 Pages View PDF
AD5666
INPUT SHIFT REGISTER
The input shift register is 32 bits wide (see Figure 42). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address
bits, A3 to A0 (see Table 9) and finally the 16-bit data-word.
The data-word comprises the 16-bit input code followed by four
don’t care bits for the AD5666 (see Figure 42). These data bits
are transferred to the DAC register on the 32nd falling edge of
SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 43).
DB31 (MSB)
DB0 (LSB)
X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
DATA BITS
SCLK
COMMAND BITS
ADDRESS BITS
Figure 42. AD5666 Input Register Content
SYNC
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
DB31
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
Figure 43. SYNC Interrupt Facility
Rev. D | Page 22 of 28
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