EVAL-AD5680DBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5680DBZ' PDF : 20 Pages View PDF
Data Sheet
THEORY OF OPERATION
DAC SECTION
The AD5680 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 23 shows a block diagram of the DAC
architecture.
DAC REGISTER
VDD
REF (+)
R
RESISTOR
STRING
R
VFB
VOUT
REF (–)
OUTPUT
AMPLIFIER
GND
Figure 23. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
V
OUT

V
REF
ï‚´

D
262,144

where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 262,143.
RESISTOR STRING
The resistor string section is shown in Figure 24. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
R
R
R
TO OUTPUT
AMPLIFIER
R
R
Figure 24. Resistor String
AD5680
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. This output
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The output amplifier’s
inverting input is available to the user, allowing for remote
sensing. This VFB pin must be connected to VOUT for normal
operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 10. The slew rate is 1.5 V/μs with a ¼ to ¾
full-scale settling time of 10 μs.
INTERPOLATOR ARCHITECTURE
The AD5680 contains a 16-bit DAC with an internal clock
generator and interpolator. The voltage levels generated by the
16-bit, 1 LSB step can be subdivided using the interpolator to
increase the resolution to 18 bits.
The 18-bit input code can be divided into two segments:
16-bit DAC code (DB19 to DB4) and 2-bit interpolator code
(DB3 and DB2). The input to the DAC is switched between a
16-bit code (for example, Code 1023) and a 16-bit code + 1 LSB
(for example, Code 1024). The 2-bit interpolator code deter-
mines the duty cycle of the switching and hence the 18-bit
code level. See Table 5 for an example.
Table 5.
18-Bit Code
DB19 to DB2
4092
4093
4094
4095
4096
16-Bit
DAC Code
DB19 to DB4
1023
1023
1023
1023
1024
2-Bit
Interpolator Code
DB3 DB2
0
0
0
1
1
0
1
1
0
0
Duty
Cycle
0
25%
50%
75%
0
The DAC output voltage is given by the average value of
the waveform switching between 16-bit code (C) and 16-bit
code + 1 (C + 1). The output voltage is a function of the duty
cycle of the switching.
18-BIT INPUT CODE
C
MUX
18
16 C + 1
16
+1
INTERPOLATOR
2
DAC
C+1
C
C+1
C
C+1
C
VOUT
FILTER
PLANT
75% DUTY CYCLE
50% DUTY CYCLE
25% DUTY CYCLE
CLK
Figure 25. Interpolation Architecture
Rev. C | Page 11 of 20
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