EVAL-AD5687RSDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5687RSDZ' PDF : 28 Pages View PDF
Data Sheet
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS
The AD5689R/AD5687R are dual 16-/12-bit, serial input,
voltage output DACs with an internal reference. The parts
operate from supply voltages of 2.7 V to 5.5 V. Data is written
to the AD5689R/AD5687R in a 24-bit word format via
a 3-wire serial interface. The devices incorporate a power-on
reset circuit to ensure that the DAC output powers up to
a known output state. The AD5689R/AD5687R also have
a software power-down mode that reduces the typical current
consumption to 4 μA.
TRANSFER FUNCTION
The internal reference is on by default. To use an external
reference, only a nonreference option is available. Because
the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
VOUT
 VREF
ï‚´ Gain
D
 2N


where:
Gain is the output amplifier gain and is set to 1 by default.
It can be set to ×1 or ×2 using the gain select pin. When the
GAIN pin is tied to GND, both DACs output a span from
0 V to VREF. If the GAIN pin is tied to VLOGIC, both DACs
output a span of 0 V to 2 × VREF.
D is the decimal equivalent of the binary code that is
loaded to the DAC register as follows: 0 to 4,095 for the
12-bit device and 0 to 65,535 for the 16-bit device.
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by
an output amplifier. Figure 41 shows a block diagram of the
DAC architecture.
VREF
2.5V
REF
INPUT
REGISTER
DAC
REGISTER
REF (+)
RESISTOR
STRING
REF (–)
VOUTX
GND
GAIN
(GAIN = 1 OR 2)
Figure 41. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 42. It is a
string of resistors, each of Value R. The code loaded to the
DAC register determines the node on the string where the
voltage is to be tapped off and fed into the output amplifier.
AD5689R/AD5687R
The voltage is tapped off by closing one of the switches
connecting the string to the amplifier. Because it is a string of
resistors, it is guaranteed monotonic.
VREF
R
R
R
TO OUTPUT
AMPLIFIER
R
R
Figure 42. Resistor String Structure
Internal Reference
The AD5689R/AD5687R on-chip reference is on at power-up
but can be disabled via a write to a control register. See the
Internal Reference Setup section for details.
The AD5689R/AD5687R have a 2.5 V, 2 ppm/°C reference,
giving a full-scale output of 2.5 V or 5 V, depending on the state
of the GAIN pin. The internal reference associated with the
device is available at the VREF pin. This buffered reference is
capable of driving external loads of up to 10 mA.
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, the offset
error, and the gain error. The GAIN pin selects the gain of the
output, as follows:
ï‚· If the GAIN pin is tied to GND, both DAC outputs have
a gain of 1, and the output range is 0 V to VREF.
ï‚· If the GAIN pin is tied to VLOGIC, both DAC outputs have
a gain of 2, and the output range is 0 V to 2 × VREF.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/μs with a ¼ to ¾ scale
settling time of 5 μs.
Rev. B | Page 19 of 28
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