EVAL-AD5687RSDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5687RSDZ' PDF : 28 Pages View PDF
Data Sheet
AD5689R/AD5687R
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD = 2.7
V to 5.5 V.
Table 5.
1.62 V ≤ VLOGIC < 2.7 V
2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Symbol Min
Max
Min
Max
Unit
SCLK Cycle Time
t1
66
40
ns
SCLK High Time
t2
33
20
ns
SCLK Low Time
t3
33
20
ns
SYNCE to SCLK Falling Edge
t4
33
20
ns
Data Setup Time
t5
5
5
ns
Data Hold Time
t6
5
5
ns
SCLK Falling Edge to SYNCE Rising Edge
t7
15
10
ns
Minimum SYNCE High Time
t8
60
30
ns
SDO Data Valid from SCLK Rising Edge
t9
45
30
ns
SYNCE Rising Edge to SCLK Rising Edge
t10
15
10
ns
SYNCE Rising Edge to SDO Disable
t11
60
60
ns
1 Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA IOL
TO OUTPUT
PIN CL
20pF
VOH (MIN)
200µA IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
t8
t4
t5
DB23
t1
24
t2
t3
t6
DB0 DB23
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
t9
48
t7
t10
DB0
UNDEFINED
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
Rev. B | Page 7 of 28
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