EVAL-AD5697RSDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5697RSDZ' PDF : 28 Pages View PDF
AD5697R
SERIAL INTERFACE
The AD5697R has a 2-wire I2C-compatible serial interface (refer
to I2C-Bus Specification, Version 2.1, January 2000, available from
Philips Semiconductor). See Figure 2 for a timing diagram of a
typical write sequence. The AD5697R can be connected to an I2C
bus as a slave device, under the control of a master device. The
AD5697R can support standard (100 kHz) and fast (400 kHz) data
transfer modes. Support is not provided for 12-bit addressing
and general call addressing.
Input Shift Register
The input shift register of the AD5697R is 24 bits wide. Data is
loaded into the device as a 24-bit word under the control of
a serial clock input, SCL. The first eight MSBs make up the
command byte. The first four bits are the command bits (C3, C2,
C1, and C0) that control the mode of operation of the device
(see Table 7). The last four bits of the first byte are the address bits
(DAC B, 0, 0, and DAC A, see Table 8).
The data-word comprises 12-bit input code, followed by four don’t
care bits for the AD5697R. These data bits are transferred to the
input register on the 24 falling edges of SCL.
Commands can be executed on individual DAC channels or
both DAC channels, depending on the address bits selected.
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
0 0 0 0 No operation
0 0 0 1 Write to Input Register n (dependent on
LDAC)
0 0 1 0 Update DAC Register n with contents of
Input Register n
0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1 Hardware LDAC mask register
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Internal reference setup register
1 0 0 0 Reserved
… … … … Reserved
1 1 1 1 Reserved
Data Sheet
Table 8. Address Commands
Address (n)
DAC B 0
0
DAC A
0
0
0
1
1
0
0
0
1
0
0
1
Description
DAC A
DAC B
DAC A and DAC B
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on LDAC)
Command 0001 allows the user to write to the dedicated input
register of each DAC individually. When LDAC is low, the input
register is transparent (if not controlled by the LDAC mask
register).
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the contents
of the input registers selected and updates the DAC outputs
directly.
Write to and Update DAC Channel n (Independent of LDAC)
Command 0011 allows the user to write to the DAC registers and
update the DAC outputs directly.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
C3 C2 C1 C0 DAC B 0
0 DAC A D11 D10 D9 D8 D7 D6 D5
DB8
D4
DB7
D3
DB6
D2
DB5
D1
DB4
D0
DB3
X
DB2
X
DB1
X
DB0
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
Figure 42. Input Shift Register Content
DATA LOW BYTE
Rev. B | Page 18 of 27
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